The term digital imaging refers to the function of a system capable of producing a digital electronic image from optical image information. Such a system is usually consisted of a matrix of pixelated optical detectors each associated with their own electronic circuits (which together are called pixels), connected to peripheral circuits (biasing, addressing, readout and digitizer circuitries).
One of the commonly used architectures for large area imaging is the passive pixel sensor (PPS) shown in FIG. 1.a. Here, a detector, for example, an amorphous selenium (a-Se) based photoconductor, a Cesium Iodide (CsI) phosphor coupled to an amorphous silicon (a-Si:H) p-i-n photodiode, or even a crystalline p-n junction, is integrated with a readout circuit comprising a transistor switch such as an a-Si:H thin-film transistor (TFT). Signal charge is accumulated on the pixel sensor during an integration cycle and is transferred to an external charge amplifier via the transistor switch, TS, during a readout/reset cycle. The transferred charge is converted to an equivalent voltage in the charge amplifier and is then further processed (using sampling and/or digitization) towards reconstruction of a digital image. It is noted that the pixel capacitance mentioned above is the p-i-n photodiode capacitance or an integrated storage capacitor for the a-Se photoconductor arrangement, or the p-n junction capacitance. Other additional analog signal processing sequences are also possible, for example, double sampling mechanisms are typically used to correct for the effect of non-uniformities within the circuitry. These non-uniformities may comprise process non-uniformities in the form of offsets, and, in the case of a-Si:H technology, non-uniformities in pixel circuit performance due to transistor instability. For example, International Patent Application Publication Nos. WO9634416 and WO9705659 further disclose flat-panel detectors for radiation imaging using PPS architecture.
While the PPS has the advantage of being compact and therefore suitable for high-resolution imaging, reading a small output signal of the PPS for low input optical signal results in a noisy voltage at the output of the charge integrator, due to the fact that charge integrators potentially add a considerable amount of noise to the input signal. This lowers the signal-to-noise ratio (SNR) at low signal levels, and thus, degrades the pixel dynamic range.
One approach for improved SNR is disclosed in International Patent Application Publication No. WO02067337 indicating that the SNR can be increased by employing in-situ, or pixel, amplification via an a-Si:H current-mediated active pixel sensor (C-APS) as depicted in FIG. 1.b. Reported gain, linearity and noise performance show an improvement and indicate that the a-Si:H C-APS, coupled with an established x-ray detection technology such as a-Se or CsI/p-i-n photodiodes, can meet the stringent requirements for low noise digital x-ray imaging for applications such as fluoroscopy, which no more than 1000 electrons of noise are allowed. In C-APS architecture, T2 is used to reset the voltage of the detector, and an on-pixel transconductance amplifier (T1) converts the detector voltage to an equivalent output current, which is then integrated in the column charge amplifier. The advantage of C-APS to PPS is the high gain; since the pixel capacitor is not discharged, a constant output current is provided as long as the row select transistor, T3, is on. Double sampling is necessary in C-APS to remove effects of non-uniformities among pixels.
Another approach disclosed in International Patent Application Publication No. WO02067337 reports a near-unity gain pixel amplifier, namely, an a-Si:H voltage-mediated active pixel sensor (V-APS). A V-APS architecture is illustrated in FIG. 1c. The pixel configuration is exactly similar to that of C-APS architecture, however, in V-APS, the pixel output is the detector voltage which is buffered out by the pixel amplifier. The advantage of V-APS over PPS and C-APS is that the charge amplifier is replaced by a simple voltage buffer. This helps less complicated design and less expensive implementation of peripheral circuits. Like the C-APS, double sampling mechanisms can be applied to the V-APS to correct for the effect of non-uniformities within the circuitry.
A difference between C-APS and V-APS is in pixel output signal, i.e., current versus voltage, the pixel circuit of both architectures (FIGS. 1.b and 1.c) is otherwise the same, and is the basic structure of active pixel architecture, comprising three field effect transistors. Other variations of the basic architectures have been reported to improve functionality of the circuit. For example, International Patent Application Publication No. WO2000019706 disclose methods of high speed resetting of the pixel, or as another example, International Patent Application Publication No. WO2006042407 introduces multimode architectures for high dynamic range, and low noise imaging applications as illustrated in FIG. 2.a; a four-transistor approach. Other non classical architectures such as two-transistor multimode architectures have also been reported in F. Taghibakhsh, K. S. Karim, “High dynamic range 2-TFT amplified pixel sensor architecture for digital mammography tomosynthesis” IET Circuits Devices & Systems, vol. 1, no. 1, pp. 87-92, (2007), and F. Taghibakhsh, K. S. Karim, “Amplified Pixel Sensor Architectures for Low Dose Computed Tomography using Silicon Thin Film Technology”, Proceedings of SPIE, vol. 6510, (2007). These architectures are shown in FIG. 2.b, where addressing each row is performed by providing a separate bias voltage for the entire row. Although such architectures provide smaller pixel size for higher imaging resolution, they require more complex peripheral circuits, and non standard driving methods. In this architecture, the row select (or read) transistor has been transferred from each pixel to its row. In all APS architectures at least three transistors are distinguished: 1) a transconductance amplifying transistor (T1) that its gate is connected to the pixel sensor/detector element, 2) a reset transistor (T2) that presets the voltage of the pixel sensor/detector element, and, and 3) a row select (or read) transistor (T3) that connects drain or source of the amplifying transistor to the imager matrix bus lines.
This background information is provided for the purpose of making known information believed by the applicant to be of possible relevance to the present invention. No admission is necessarily intended, nor should be construed, that any of the preceding information constitutes prior art against the present invention.